Renesas ISL6614CR

Tube Half-Bridge Non-Inverting Synchronous gate driver 26ns 18ns 0C~125C TJ 1.25A 2A 36V

Half Bridge MOSFET 1.25A 10.8V~13.2V 2A QFN-16(4x4) Gate Drive ICs ROHS

Driver 3A 4-OUT High and Low Side Half Brdg Inv/Non-Inv 16-Pin QFN EP

Operation Designed for versatility and speed, the ISL6614 MOSFET driver controls both high-side and low-side N-Channel FETs of two half-bridge power trains from two externally provided PWM signals. Prior to VCC exceeding its POR level, the Pre-POR over voltage protection function is activated; the upper gate (UGATE) is held low and the lower gate (LGATE), controlled by the Pre-POR over voltage protection circuits, is connected to the PHASE. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [t PDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the PHASE voltage and determines the upper gate delay time [tPDHU]. This prevents both the lower and upper MOSFETs from conducting simultaneously. Once this delay period is complete, the upper gate drive begins to rise [tRU] and the upper MOSFET turns on. A falling transition on PWM results in the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [t PDLU] is encountered before the upper gate begins to fall [tFU]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, t PDHL. The PHASE voltage and the UGATE voltage are monitored, and the lower gate is allowed to rise after PHASE drops below a level or the voltage of UGATE to PHASE reaches a level depending upon the current direction (See next section for details). The lower gate then rises [t RL], turning on the lower MOSFET. Advanced Adaptive Zero Shoot-Through Dead time Control (Patent Pending) These drivers incorporate a unique adaptive dead time control technique to minimize dead time, resulting in high efficiency from the reduced freewheeling time of the lower MOSFETs' body-diode conduction, and to prevent the upper and lower MOSFETs from conducting simultaneously. This is accomplished by ensuring either rising gate turns on its MOSFET with minimum and sufficient delay after the other has turned off. During turn-off of the lower MOSFET, the PHASE voltage is monitored until it reaches a -0.2V/+0.8V trip point for a forward/reverse current, at which time the UGATE is released to rise. An auto-zero comparator is used to correct the rDS(ON) drop in the phase voltage preventing from false detection of the -0.2V phase level during r DS(ON conduction period. In the case of zero current, the UGATE is released after 35ns delay of the LGATE dropping below 0.5V. During the phase detection, the disturbance of L Gate's falling transition on the PHASE node is blanked out to prevent falsely tripping. Once the PHASE is high, the advanced adaptive shoot-through circuitry monitors the PHASE and UGATE voltages during a PWM falling edge and the subsequent UGATE turn-off. If either the UGATE falls to less than 1.75V above the PHASE or the PHASE falls to less than +0.8V, the LGATE is released to turn on. Three-State PWM Input A unique feature of these drivers and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set hold off time, the driver outputs are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled. This feature helps prevent a negative transient on the output voltage when the output is shut down, eliminating the Schottky diode that is used in some systems for protecting the load from reversed output voltage events.