Texas Instruments SN74V263-15PZA

FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18/16K x 9 80-Pin LQFP Tray
$ 14.58
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Newark

Datasheet52 pagesIl y a 16 ans

Texas Instruments

DigiKey

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Pièces détachées

Texas InstrumentsSN74V263PZAEP
Enhanced Product 8192 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Texas InstrumentsSN74V273-7PZA
FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 80-Pin LQFP Tray
QUAD COMMERCIAL Synchronous PARALLEL (Function) FIFO 0C 3.6V 512B 15ns
Texas InstrumentsSN74V273PZAEP
Enhanced Product 16384 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Synchronous FIFO 72K (4K x 18) Uni-Directional 66.7MHz 10ns 64-TQFP (10x10)
QUAD COMMERCIAL PARALLEL Tin (Function) FIFO 0C 3.6V 2.3kB 10ns

Descriptions

Descriptions de Texas Instruments SN74V263-15PZA fournies par ses distributeurs.

FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18/16K x 9 80-Pin LQFP Tray
8192 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:80-LQFP; No. of Pins:80; Operating Temperature Range:0°C to +70°C; Peak Reflow Compatible (260 C):No ;RoHS Compliant: Yes
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching *9/*18 data flow. There is flexible *9/*18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins' input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Copyright (C) 2003, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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