Texas Instruments SN74ALS561ADW

Tube Obsolete 74ALS561 TCO OUTPUT; COUNT ENABLE INPUTS logic counter 18ns 7.5mm 5V 0.008A
$ 2.644
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Datasheet15 pagesIl y a 18 ans

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Pièces de rechange

Price @ 1000
$ 2.644
$ 3.184
Stock
91,202
84,939
Authorized Distributors
2
2
Case/Package
SOIC
SOIC
Number of Pins
20
20
Logic Function
Counter
Counter
Direction
Down
Down
Number of Elements
1
1
Number of Bits per Element
4
4
Reset
Asynchronous, Synchronous
Asynchronous, Synchronous
Clock Edge Trigger Type
Positive Edge
Positive Edge
Frequency
30 MHz
30 MHz
Min Supply Voltage
4.5 V
-
Max Supply Voltage
5.5 V
-

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Descriptions

Descriptions de Texas Instruments SN74ALS561ADW fournies par ses distributeurs.

Tube Obsolete 74ALS561 TCO OUTPUT; COUNT ENABLE INPUTS logic counter 18ns 7.5mm 5V 0.008A
LOGIC,COUNTER BIN 4BIT SYNCH,20SOIC; Logic IC Function:4-Bit Synchronous Binary Counter with 3-State Outputs; Logic IC Family:ALS; Logic IC Base Number:74561; Max Clock Frequency:30MHz; Max Count:16; Counter Function:Synchronous Binary Counter; Min Supply Voltage:4.5V; Max Supply Voltage:5.5V; Case Style:SOIC; Operating Temperature Range:0°C to +70°C; No. of Pins:20; Termination Type:SMD
These binary counters are programmable and offer synchronous and asynchronous clearing as well as synchronous and asynchronous loading. All synchronous functions are executed on the positive-going edge of the clock. The clear function is initiated by applying a low level to either asynchronous clear (ACLR\) or synchronous clear (SCLR\). ACLR\ (direct clear) overrides all other functions of the device, while SCLR\ overrides only the other synchronous functions. Data is loaded from the A, B, C, and D inputs by applying a low level to asynchronous load (ALOAD\) or by the combination of a low level at synchronous load (SLOAD\) and a positive-going clock transition. The counting function is enabled only when enable P (ENP), enable T (ENT), ACLR\, ALOAD\, SCLR\, and SLOAD\ are all high. A high level at the output-enable () input forces the Q outputs into the high-impedance state, and a low level enables those outputs. Counting is independent of OE\. ENT is fed forward to enable the ripple-carry output (RCO) to produce a high-level pulse while the count is maximum (15). The clocked carry output (CCO) produces a high-level pulse for a duration equal to that of the low level of the clock when RCO is high and the counter is enabled (ENP and ENT are high); otherwise, CCO is low. CCO does not have the glitches commonly associated with a ripple-carry output. Cascading is normally accomplished by connecting RCO or CCO of the first counter to ENT of the next counter. However, for very high-speed counting, RCO should be used for cascading because CCO does not become active until the clock returns to the low level. The SN54ALS561A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS561A is characterized for operation from 0°C to 70°C.

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