Texas Instruments SN74V293-15PZA

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
$ 40.862
Production

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Newark

Datasheet52 páginasHace 17 años

Texas Instruments

Sierra IC

Arrow Electronics

Historial de existencias

Tendencia de 3 meses:
+82.03%

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Componentes alternativos

Price @ 1000
$ 40.862
$ 37.148
Stock
119,619
56,436
Authorized Distributors
1
0
Case/Package
LQFP
LQFP
Number of Pins
80
80
Memory Size
144 kB
144 kB
Access Time
10 ns
10 ns
Frequency
66.7 MHz
66.7 MHz
Bus Directional
Unidirectional
Unidirectional
Programmable Flags Support
Yes
Yes
Retransmit Capability
Yes
Yes
FWFT Support
Yes
Yes
Min Supply Voltage
3.15 V
3.15 V
Max Supply Voltage
3.45 V
3.45 V

Cadena de suministros

Lifecycle StatusProduction (Last Updated: 3 days ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 3 days ago)

Componentes relacionados

Texas InstrumentsSN74V263-15PZA
FIFO Mem Sync Dual Depth/Width Uni-Dir 8K x 18/16K x 9 80-Pin LQFP Tray
Texas InstrumentsSN74V283-15PZA
FIFO Mem Sync Dual Depth/Width Uni-Dir 32K x 18/64K x 9 80-Pin LQFP Tray
Texas InstrumentsSN74V273-15PZA
FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 80-Pin LQFP Tray
QUAD PARALLEL GULL WING Synchronous Synchronous FIFO 0C~70C 3.6V 288K 16K x 18 66.7MHz

Descripciones

Descripciones de Texas Instruments SN74V293-15PZA suministradas por sus distribuidores.

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
ACTIVE (Last Updated: 1week ago) 74V293 Depth Width Tray fifo memory 66.7MHz 35mA 0.65mm 15ns
65536 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:80-LQFP; No. of Pins:80; Operating Temperature Range:0°C to +70°C; Peak Reflow Compatible (260 C):No ;RoHS Compliant: Yes
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching *9/*18 data flow. There is flexible *9/*18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins' input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Copyright (C) 2003, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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