onsemi MC100LVEL32DG

MC100LVEL32 Series 3.3 V Surface Mount ECL ÷ 2 Divider - SOIC-8

MC100LVEL32DG, CLOCK DIVIDER ECL ECL 1-INPUT DIFFERENTIAL 8-PIN SOIC

Clock Divider Buffer 1-OUT 1-IN 1:1 8-Pin SOIC N Tube

Tube Active e3 100LVEL32 divider circuit 680ps 2000 4mm -3.3V

Clock Drivers & Distribution 3.3V ECL Divide By 2 Divider

ON Semiconductor ECL series 1Input clock divider clock divider, ECLoutput, Differential mode, 8Pin SOICencapsulation

Amplifiers- Audio 3.3V ECL Divide By 2 Divider

3V~3.8V 1 1 2.6GHz SOP-8 Counters / Dividers ROHS

IC,MC100LVEL32DG,BBG ECL DIFF INPUT 2 DIV PB-FREE<AZ

Prescaler, 100LVEL Series, 1-Func, ECL, PDSO8

IC DIVIDER DIV X2 ECL 3.3V 8SOIC

IC, ECL 100, SMD, 100LVEL32, SOIC8; Supply Voltage Range:± 3V to ± 3.8V; Logic Case Style:SOIC; No. of Pins:8; Operating Temperature Range:-40°C to +85°C; SVHC:No SVHC (19-Dec-2011); Base Number:100LVEL32; Clock Frequency Max:2.6GHz; IC Generic Number:100LVEL32; Logic Function Number:32; Logic IC Base Number:10032; Logic IC Family:ECL; Logic IC Function:Ecl ÷2 Divider; Operating Temperature Max:85°C; Operating Temperature Min:-40°C; Package / Case:SOIC; Supply Voltage:3.3V; Supply Voltage Max:3.8V; Supply Voltage Min:3V; Termination Type:SMD

The MC100LVEL32 is an integrated w2 divider. The LVEL32 is functionally identical to the EL32 but operates from a 3.3 V supply. The reset pin is asynchronous and is asserted on the rising edge. Upon power-up the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple LVEL32s in a system. The VBB pin an internally generated voltage supply is available to this device only. For single-ended input conditions the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used VBB should be left open.