Texas Instruments SN74F161AN

Synchronous 4-Bit Binary Counter 16-PDIP 0 to 70

Synchronous Positive Edge Asynchronous Synchronous divider circuit 0C~70C 100MHz 5V 6.35mm

Logic IC Operating temperature: 0...+70 °C Series: SN74F161 Function: 4-Bit / Decade / Counter Manufacturer: Texas Instruments Package: DIL-16 Technology: F

LOGIC, SYNC 4-BIT BIN CNTR, 16DIP; Logic Family / Base Number: 74F161; Counter Type: Binary, Synchronous; Clock Frequency: 120MHz; Count Maximum: 16; Logic Case Style: DIP; No. of Pins: 16Pins; Supply Voltage Min: 4.5V; Supply Voltage Max: 5.5V; Logic IC Family: 74F; Logic IC Base Number: 74161; Operating Temperature Min: 0°C; Operating Temperature Max: 70°C; Product Range: -; RoHS Phthalates Compliant: Yes; MSL: -; SVHC: No SVHC (27-Jun-2018); Logic IC Base Number: 74161; Logic IC Function: 4bit Synchronous Binary Counter; Operating Temperature Range: 0°C to +70°C; Supply Voltage Range: 4.5V to 5.5V; Termination Type: Through Hole

This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK. This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT. The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop outputs to low, regardless of the levels of CLK, LOAD, ENP, and ENT. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces ahigh-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. The SN74F161A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold times.