Texas Instruments SN74ALS232BFN

74ALS232 Width Tube 8542.32.00.71 fifo memory 40MHz 125mA 1.27mm 25ns
$ 4.016
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Texas Instruments

Datasheet12 SeitenVor 18 Jahren

Newark

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Price @ 1000
$ 4.016
$ 2.014
Stock
143,992
95,662
Authorized Distributors
2
2
Case/Package
PLCC
LCC
Number of Pins
20
20
Memory Size
-
8 B
Access Time
-
-
Frequency
40 MHz
40 MHz
Bus Directional
-
-
Programmable Flags Support
-
-
Retransmit Capability
-
-
FWFT Support
-
-
Min Supply Voltage
-
4.5 V
Max Supply Voltage
-
5.5 V

Beschreibungen

Beschreibungen von Texas Instruments SN74ALS232BFN, die von den Distributoren bereitgestellt werden.

74ALS232 Width Tube 8542.32.00.71 fifo memory 40MHz 125mA 1.27mm 25ns
FIFO Logic IC; Logic Family:ALS; Frequency Max:50MHz; Supply Voltage Min:4.5V; Supply Voltage Max:5.5V; Package/Case:20-PLCC; No. of Pins:20; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No
This 64-bit memory features high speed and fast fall-through times. It is organized as 16 words by 4 bits. A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array at independent data rates. This FIFO is designed to process data at rates up to 40MHz in a bit-parallel format, word by word. Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory is empty, UNCK signals have no effect. Status of the FIFO memory is monitored by the FULL\ and EMPTY\ output flags. The FULL\ output is low when the memory is full and high when it is not full. The EMPTY\ output is low when the memory is empty and high when it is not empty. A low level on the reset (RST\) input resets the internal stack-control pointers and also sets EMPTY\ low and sets FULL\ high. The Q outputs are not reset to any specific logic level. The first low-to-high transition on LDCK, after either a RST\ pulse or from an empty condition, causes EMPTY\ to go high and the data to appear on the Q outputs. It is important to note that the first word does not have to be unloaded. Data outputs are noninverting with respect to the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the FULL\ or EMPTY\ output flags. Cascading is easily accomplished in the word-width direction but is not possible in the word-depth direction. The SN74ALS232B is characterized for operation from 0C to 70C.

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