onsemi MC100E131FNG

Flip Flop D-Primary-Secondary Type Pos-Edge 1-Element 28-Pin PLCC Rail

Tube 100E131 e3 100E flip flop 1.4GHz 675ps -4.2V~-5.7V 70mA

D Flip-Flop, 100E Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, ECL, PQCC28

-5.7V~-4.2V D-Type 4 1 1.4GHz 70mA PLCC-28 Flip Flops ROHS

IC FF D-TYPE SGL 4-BIT 28-PLCC

D-Type Flip Flop Quad, 0.5Ns Plcc-28; Logic Family/Base Number:-; Flip-Flop Type:D; Propagation Delay:500Ps; Frequency:1.4Ghz; Output Current:50Ma; Logic Case Style:Lcc; No. Of Pins:28Pins; Trigger Type:Positive Edge Rohs Compliant: Yes |Onsemi MC100E131FNG

The MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (CEbar) inputs for clocking. Common clocking is achieved by holding the CEbar inputs LOW and using CC to clock all four flip-flops. In this case the CEbar inputs perform the function of controlling the common clock to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CEbar are LOW and transfers to the slave when either CC or CEbar (or both) go HIGH. The 100 Series contains temperature compensation.