onsemi 74VHC373MTCX

74VHC Series High Speed CMOS Octal D-Type Latch w/ 3-STATE Output - TSSOP-20
$ 0.373
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Datenblätter und Dokumente

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Fairchild Semiconductor

Datasheet9 SeitenVor 19 Jahren
Technical Drawing1 SeiteVor 18 Jahren

Master Electronics

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DigiKey

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Alternative Teile

Price @ 1000
$ 0.373
$ 0.479
$ 0.479
Stock
447,970
315,403
315,403
Authorized Distributors
6
6
6
Case/Package
TSSOP
TSSOP
TSSOP
Number of Pins
20
20
20
Logic Function
D-Type, Latch
D-Type, Latch
D-Type, Latch
Number of Elements
1
1
1
Number of Bits per Element
-
-
-
Propagation Delay
10.5 ns
10.5 ns
10.5 ns
Frequency
-
-
-
Clock Edge Trigger Type
-
-
-
Min Supply Voltage
2 V
2 V
2 V
Max Supply Voltage
5.5 V
5.5 V
5.5 V
Quiescent Current
4 µA
4 µA
4 µA

Lieferkette

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1995-01-01
Lifecycle StatusProduction (Last Updated: 5 years ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

Verwandte Teile

Texas InstrumentsSN74AHC373PWR
4¦ÌA 1ns 1 2V 5.5V 8mA D-Type Transparent Latch AHC 1 8mA TSSOP-20 , 6.5mm*4.4mm*1.15mm
74AHC Series 5 V SMT Positive-Edge Trigger Octal D-Type Flip-Flop - TSSOP-20
Texas InstrumentsSN74AHC273PWR
Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R
4¦ÌA 4.5ns 1 2V 5.5V 8mA D-Type Transparent Latch VHC 1 8mA TSSOP-20 6.5mm*4.4mm*1.2mm
Texas InstrumentsSN74AHC574PWR
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-TSSOP -40 to 125
D Flip-Flop, AHC/VHC Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20

Beschreibungen

Beschreibungen von onsemi 74VHC373MTCX, die von den Distributoren bereitgestellt werden.

74VHC Series High Speed CMOS Octal D-Type Latch w/ 3-STATE Output - TSSOP-20
4¦ÌA 5ns 1 2V 5.5V 8mA D-Type Latch VHC 1 8mA TSSOP-20 , 6.5mm*4.4mm*900¦Ìm
74VHC373 Tape & Reel (TR) AHC/VHC 74VHC latch circuit 8mA 8mA 17ns 191mg -40C~85C
The VHC373 is an advanced high speed CMOS octal D-type latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an output enable input (OE#). The latches appear transparent to data when latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is LATCHED. When the OE# input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.

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