these synchronous presettable 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable ( ) inputs and internal gating. this mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. a buffered clock (clk) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform. these counters are fully programmable; they may be preset to any number between 0 and 255. the load-input circuitry allows parallel loading of the cascaded counters. view all in datasheet