Texas Instruments CDCLVP110

the cdclvp110 clock driver distributes one differential clock pair of either lvpecl or hstl (selectable) input (clk0 clk1) to ten pairs of differential lvpecl clock (q0 q9) outputs with minimum skew for clock distribution. the cdclvp110 can accept two clock sources into an input multiplexer. the clk0 input accepts either lvecl/lvpecl input signals while clk1 accepts an hstl input signal when operated under lvpecl conditions. the cdclvp110 is specifically designed for driving 50- transmission lines. the vbb reference voltage output is used if single-ended input operation is required. in this case the vbb pin should be connected to clk0 and bypassed to gnd via a 10-nf capacitor. however for high-speed performance up to 3. view all in datasheet