Texas Instruments CDC536

the cdc536 is a high-performance low-skew low-jitter clock driver. it uses a phase-lock loop (pll) to precisely align in both frequency and phase the clock output signals to the clock input (clkin) signal. it is specifically designed for use with synchronous drams and popular microprocessors operating at speeds from 50 mhz to 100 mhz or down to 25 mhz on outputs configured as half-frequency outputs. the cdc536 operates at 3.3-v vcc and is designed to drive a 50-w transmission line. the feedback input (fbin) is used to synchronize the output clocks in frequency and phase to the input clock (clkin). one of the six output clocks must be fed back to fbin for the pll to maintain synchronization between clkin and the outputs. view all in datasheet