Texas Instruments CD74HC652EN

High Speed CMOS Logic Octal Bus Transceiver/Registers with 3-State Outputs 24-PDIP -55 to 125

Registered Bus Transceiver, HC/UH Series, 1-Func, 8-Bit, True Output, CMOS, PDIP24

LOGIC, TRANSCVR TRI-ST OCTAL, 24DIP; Logic Device Type:Transceiver, Non Inverting; Supply Voltage Range:2V to 6V; Logic Case Style:DIP; No. of Pins:24; Operating Temperature Range:-55°C to +125°C; SVHC:No SVHC (20-Jun-2011); Logic Function Number:74652; Logic IC Base Number:74652; Logic IC Family:HC; Logic IC Function:Octal-Bus Transceiver / Register with 3-State Outputs; Package / Case:PDIP; Supply Voltage Max:6V; Supply Voltage Min:2V; Termination Type:Through Hole

The CD74HC652 and CD74HCT652 three-state, octal-bustransceiver/registers use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. The CD74HC652 and CD74HCT652 have non-inverting outputs. These devices consists of bus transceiver circuits, D-type flipflops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEAB and OEBAare provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in amultiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a High selects stored data. The following examples demonstrates the four fundamentals bus-management functions that can be performed with the octal-bus transceivers and registers. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select of the control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the D-type flip-flops by simultaneously enabling OE AB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines will remain at its last state.