供应链
Export Control Classification Number (ECCN) CodeNLR
Harmonized Tariff Schedule (HTS) Code8540000000
Introduction Date1988-01-01
Lifecycle StatusObsolete (Last Updated: 2 months ago)
LTB Date2018-06-15
LTD Date2018-09-15
Manufacturer Lifecycle StatusOBSOLETE (Last Updated: 2 months ago)
描述
由其分销商提供的 Renesas 7201LA50P 的描述。
FIFO Mem Async Dual Depth/Width Uni-Dir 512 x 9 28-Pin PDIP
FIFO, 512X9, 50ns, Asynchronous, CMOS, PDIP28
IC FIFO ASYNC 512X9 50NS 28DIP
IC 8BIT LATCH W/3ST OUT 20-QSOP
制造商别名
Renesas 在全球拥有多个品牌，分销商可将其用作替代名称。Renesas 也可称为以下名称：
- Renesas Electronics
- Renesas Electronics America Inc
- Renesas Electronics America
- RENESA
- REN
- RENES
- RENESAS TECHNOLOGY CORP
- RENESAS TECHNOLOGY
- Renesas Electronics Corporation
- RENESAS ELECTRONICS CORP
- RENSAS
- RENASAS
- Renesas / Intersil
- RNS
- RENESAS-PB
- RENESASTEC
- RENESES
- Renesas Technology America
- Renesas Design Germany GmbH
- Renesas / IDT
- RENESASE
- RENESAS TECHNOLOGY HONG KONG
- Renesas Electronics Operations Services Limited
- RENEASAS
- RENESAS/M
技术规格
Physical
Case/PackagePDIP
Contact PlatingLead, Tin
MSL1
MountThrough Hole
Number of Pins28
Number of Terminals28
Technical
Access Time50 ns
Bus DirectionalUnidirectional
Cycle Time65 ns
Data Bus Width9 b
Density4.5 kb
DirectionUnidirectional
Element ConfigurationDual
Part Family7201
FWFT SupportNo
InterfaceParallel
Max Frequency15.38 MHz
Max Operating Temperature70 °C
Max Supply Current80 mA
Max Supply Voltage5.5 V
Memory Size512 B
Min Operating Temperature0 °C
Min Supply Voltage4.5 V
Nominal Supply Current80 mA
Number of Circuits1
Operating Supply Voltage5 V
Package Quantity0
Programmable Flags SupportNo
Retransmit CapabilityYes
Sync/AsyncAsynchronous
Temperature GradeCommercial
Word Size9 b
Dimensions
Height3.8 mm
Height - Seated (Max)4.699 mm
Length36.6 mm
Pitch2.54 mm
Terminal Pitch2.54 mm
Thickness3.8 mm
Width15.24 mm