onsemi 100331QCX

Master Reset D-Type ECL Positive Edge Flip Flop 0C~85C TC 50mA -4.2V~-5.7V 1.4ns

Flip Flop D-Primary-Secondary Type Pos-Edge 1-Element 28-Pin PLCC T/R

D Flip-Flop, 100K Series, 3-Func, Positive Edge Triggered, 1-Bit, Complementary Output, ECL, PQCC28

-5.7V~-4.2V D-Type 1 3 400MHz PLCC-28(11.5x11.5) Flip Flops ROHS

The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CPn and CPC are LOW and transfers to a slave when CPn or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kohm pull-down resistors. Product Highlights: 35% power reduction of the 100131 2000V ESD protection Pin/function compatible with 100131 Voltage compensated operating range = -4.2V to -5.7V Available to industrial grade temperature range