供应链
Harmonized Tariff Schedule (HTS) Code8542.31.00.55
Introduction Date1991-11-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2017-06-01
LTD Date2017-12-01
描述
由其分销商提供的 Intel / Altera EPM7160STC100-6N 的描述。
CPLD MAX 7000S Family 3.2K Gates 160 Macro Cells 149.3MHz CMOS Technology 5V 100-Pin TQFP
ALTERA EPM7160STC100-6N CPLD, MAX 7000, 160 MCELLS, 100TQFP
EE PLD, 6ns, 160-Cell, CMOS, PQFP100
CPLD, MAX 7000, 160 MCELLS, 100TQFP; CPLD Type: EEPROM; No. of Macrocells: 160; No. of I/O's: 84I/O's; Logic Case Style: TQFP; No. of Pins: 100Pins; Frequency: 166.7MHz; Supply Voltage Min: 4.75V; Supply Voltage Max: 5.25V; Prop
制造商别名
Intel / Altera 在全球拥有多个品牌，分销商可将其用作替代名称。Intel / Altera 也可称为以下名称：
- Altera (Intel)
- Altera (Intel Programmable Solutions Group)
- Intel FPGAs/Altera
- ALTERA CORP
- Intel Corporation
- IntelProgrammable Solutions Group
- Intel / Alte
- INTEL CORP
- ALTERA CORPORATION
- ALTERAINERNATIONALLIMITED
技术规格
Physical
Case/PackageLFQFP
MountSurface Mount
Number of Pins100
Number of Terminals100
Technical
Frequency166.7 MHz
Max Frequency166.7 MHz
Max Operating Temperature70 °C
Max Supply Voltage5.25 V
Memory TypeEEPROM
Min Operating Temperature0 °C
Min Supply Voltage4.75 V
Number of Gates3200
Number of I/Os84
Number of Inputs84
Number of Logic Blocks (LABs)10
Number of Logic Elements/Cells10
Number of Macrocells160
Number of Outputs84
Number of Programmable I/O84
Operating Supply Voltage5 V
Propagation Delay6 ns
Schedule B8542390000
Speed Grade6
Temperature GradeCommercial
Turn-On Delay Time6 ns
Dimensions
Height - Seated (Max)1.27 mm
Length14 mm
Terminal Pitch500 µm
Width14 mm