Texas Instruments SN74ACT7802-60FN

1024 X 18 asynchronous FIFO memory 68-PLCC 0 to 70

74ACT7802 Width Tube 74ACT fifo memory 16.7MHz 400muA 4.57mm 60ns

FIFO Mem Async Dual Width Uni-Dir 1K x 18 68-Pin PLCC

1K X 18 OTHER FIFO 45 ns PQCC68

IC FIFO ASYNC 1KX18 45NS 68PLCC

IC STROBED FIFO 1024X18 68-PLCC

FIFO, 1KX18, 45NS, SYNCHRONOUS

1024 × 18 STROBED FIRST-IN, FIRST-OUT MEMORY

A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ACT7802 is a 1024-word by 18-bit FIFO for high-speed applications. It processes data in a bit-parallel format at rates up to 40 MHz and access times of 30 ns. Data is written into the FIFO memory on a low-to-high transition on the load-clock (LDCK) input and is read outon a low-to-high transition on the unload-clock (UNCK) input. The memory is full when the number of words clocked in exceeds by 1024 the number of words clocked out. When the memory is full, LDCK has no effect onthe data in the memory; when the memory is empty, UNCK has no effect. A low level on the reset (RESET) input resets the FIFO internal clock stack pointers and sets full (FULL) high,almost full/almost empty (AF/AE) high, half full (HF) low, and empty (EMPTY) low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power up. The Q outputs are non inverting and are inthe high-impedance state when the output-enable (OE) input is low. When writing to the FIFO after a reset pulse or when the FIFO is empty, the first active transition on LDCK drives Empty high and causes the first word written to the FIFO to appear on the Q outputs. An active transition on UNCK is not required to read the first word written to the FIFO. Each subsequent read from the FIFO requires an active transition on UNCK. The SN74ACT7802 can be cascaded in the word-width direction but not in the word-depth direction. The SN74ACT7802 is characterized for operation from 0oC to 70oC.