Texas Instruments SA555

these devices are precision timing circuits capable of producing accurate time delays or oscillation. in the time-delay or monostable mode of operation the timed interval is controlled by a single external resistor and capacitor network. in the astable mode of operation the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor. the threshold and trigger levels normally are two-thirds and one-third respectively of vcc. these levels can be altered by use of the control-voltage terminal. when the trigger input falls below the trigger level the flip-flop is set and the output goes high. if the trigger input is above the trigger level and the threshold input is above the threshold level the flip-flop is reset and the output is low. view all in datasheet