Texas Instruments CD40192BPWR

4000/14000/40000 Series Syn Positive Edge Triggered 4-BIT Bidirectional Decade Counter PDSO16

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Texas Instruments

Datasheet14 páginas18 anos atrás

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Peças alternativas

Price @ 1000
$ 0.247
Stock
43,296
185,995
Authorized Distributors
0
5
Case/Package
TSSOP
TSSOP
Number of Pins
16
16
Logic Function
Counter
Counter
Direction
-
Bidirectional
Number of Elements
1
1
Number of Bits per Element
4
4
Reset
Asynchronous
Asynchronous
Clock Edge Trigger Type
Positive Edge
Positive Edge
Frequency
-
11 MHz
Min Supply Voltage
-
3 V
Max Supply Voltage
-
18 V

Descrições

Descrições de Texas Instruments CD40192BPWR fornecidas pelos seus distribuidores.

4000/14000/40000 SERIES SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER PDSO16
Logic - Counters CMOS Presettable BCD Up/Down Counter
IC DECADE COUNTER 4-BIT 16TSSOP
IC UP/DOWN COUNTR PRESET 16TSSOP
CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided. The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low. The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY\ and BORROW\ signals are high with the counter is counting up or down. The CARRY\ signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW\ signal goes low one-half clock cycle after the counter reaches its minimum count in the count-down mode. Cascading of multiple packages is easily accomplished with out the need for additional external circuitry by tying the BORROW\ and CARRY\ outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package. The CD40192B and CD40193B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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