onsemi 74LVX273MX

Lead Free Master Reset D-Type CMOS Flip Flop -40C~85C TA 4muA 4pF 2V~3.6V

2V~3.6V 90MHz 14.5ns@3.3V,50pF D-Type 8 1 4uA SOIC-20 Flip Flops ROHS

FLIP FLOP D-TYPE BUS INTRFC POS-EDGE 1-ELEM 20SOIC W

D Flip-Flop, LV/LV-A/LVX/H Series, 8-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO20

Low Voltage Octal D-Type Flip-Flop

The LVX273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR#) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR# input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.