Texas Instruments SN74V293-6PZA

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
$ 39.094
Production

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Texas Instruments SN74V293-6PZA에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

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Datasheet52 페이지16년 전

Texas Instruments

Augswan

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3개월간의 트렌드:
-79.96%

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공급망

Lifecycle StatusProduction (Last Updated: 1 day ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 1 day ago)

관련 부품

Texas InstrumentsSN74V293PZAEP
Enhanced Product 65536 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Texas InstrumentsV62/03639-04XE
Enhanced Product 65536 X 18 Synchronous Fifo Memory 80-LQFP -55 to 125
Texas InstrumentsSN74V263-6PZA
ACTIVE (Last Updated: 1week ago) 74V263 Depth Width Tray fifo memory 166MHz 35mA 0.65mm 6ns
4Kx18 6.5ns 30mA 3V~3.6V 100MHz TQFP-64(10x10) FIFO Memory ROHS
QUAD COMMERCIAL PARALLEL Tin (Function) FIFO 0C 3.6V 2.3kB 10ns
Synchronous FIFO 72K (4K x 18) Uni-Directional 66.7MHz 10ns 64-TQFP (10x10)

설명

유통업체에서 제공한 Texas Instruments SN74V293-6PZA에 대한 설명입니다.

FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 18/128K x 9 80-Pin LQFP Tray
ACTIVE (Last Updated: 2days ago) 74V293 Depth Width Tray fifo memory 166MHz 35mA 0.65mm 6ns
4.5ns 128Kx9 35mA 3.15V~3.45V 166MHz LQFP-80(14x14) FIFO Memory ROHS
65536 x 18 Synchronous FIFO Memory 80-LQFP 0 to 70
The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching *9/*18 data flow. There is flexible *9/*18 bus matching on both read and write ports. The period required by the retransmit operation is fixed and short. The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can beread, is fixed and short. These FIFOs are particularly appropriate for network, video, telecommunications, data communications, andother applications that need to buffer large amounts of data and match buses of unequal sizes. Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bitor 9-bit width, as determined by the state of external control pins' input width (IW) and output width (OW) during the master-reset cycle. The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. An output-enable (OE) input is provided for 3-state control of the outputs. Copyright (C) 2003, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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