Texas Instruments SN74V235-15PAG

ACTIVE (Last Updated: 6days ago) 74V235 Depth Width Tray fifo memory 66.7MHz 35mA 0.5mm 15ns

2048 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70

FIFO Mem Sync Dual Depth/Width Uni-Dir 2K x 18 64-Pin TQFP Tray

FIFO Logic IC; Frequency Max:133MHz; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Package/Case:64-TQFP; No. of Pins:64; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:Yes; Operating Temp. Max:70°C ;RoHS Compliant: Yes

IC, SYNC FIFO MEMORY, SMD, TQFP64; FIFO Function:Asynchronous; Access Time:10ns; Frequency:66.7MHz; Memory Organisation:2048 x 18bit; Supply Voltage Range:3V to 3.6V; Logic Case Style:TQFP; No. of Pins:64; Operating Temperature Range:0°C to +70°C; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2011); Base Number:74; IC Temperature Range:Commercial; Logic Function Number:74V235; Logic IC Base Number:74235; Logic IC Family:V; Logic IC Function:18 Synchronous FIFO Memory; Memory Size:2048-Word x 18bit; Operating Temperature Max:70°C; Operating Temperature Min:0°C; Package / Case:TQFP; Packaging Type:Peel Pack; Supply Voltage:3.3V; Supply Voltage Max:3.6V; Supply Voltage Min:3V; Termination Type:SMD

The SN74V215, SN74V225, SN74V235, and SN74V245 are very high-speed, low-power CMOS clocked first-in first-out (FIFO) memories. They support clock frequencies up to 133 MHz and have read-access times as fast as 5 ns. These DSP-Sync (TM) FIFO memories feature read and write controls for use in applications such asDSP-to-processor communication, DSP-to-analog front end (AFE) buffering, network, video, and data communications. These are synchronous FIFOs, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between DSPs, microprocessors, and/or buses controlled by a synchronous interface. An output-enable (OE) input controls the 3-state output. The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR),and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). Ahalf-full flag (HF) is available when the FIFO is used in a single-device configuration. Two timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and standard mode. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word. In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless aspecific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines. These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins areused to expand the FIFOs. In depth-expansion configuration, first load (FL) is grounded on the first device and set to high for all other devices in the daisy chain. The SN74V215, SN74V225, SN74V235, and SN74V245 are characterized for operation from 0oC to 70oC. Copyright (C) 2002, Texas Instruments Incorporated Production DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.