Texas Instruments SN54LS76A

the 76 contains two independent j-k flip-flops with individual j-k clock preset and clear inputs. the 76 is a positive-edge-triggered flip-flop. j-k input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. for these devices the j and k inputs must be stable while the clock is high. the ls76a contain two independent negative-edge-triggered flip-flops. the j and k inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. the preset and clear are asynchronous active low inputs. when low they override the clock and data inputs forcing the outputs to the steady state levels as shown in the function table. view all in datasheet