Texas Instruments DS92LV010ATM

BUS LVDS 3.3/5.0V SINGLE TRANSCEIVER Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, CMOS, PDSO8
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Datasheet17 페이지12년 전

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공급망

Lifecycle StatusProduction (Last Updated: 1 year ago)
Manufacturer Lifecycle StatusLIFEBUY (Last Updated: 1 year ago)

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설명

유통업체에서 제공한 Texas Instruments DS92LV010ATM에 대한 설명입니다.

BUS LVDS 3.3/5.0V SINGLE TRANSCEIVER Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, CMOS, PDSO8
BUS TRANCEIVER LVDS, SMD, 92LV010; Supply Voltage Range:3V to 3.6V, 4.5V to 5.5V; Operating Temperature Range:-40°C to +85°C; No. of Pins:8; SVHC:No SVHC (19-Dec-2011); Base Number:92; Data Rate:100Mbps; IC Generic Number:92LV010; Interface Type:3.3V LVDS; Line / Bus Driver / Receiver / Transceiver Type:3.3V LVDS; Logic Case Style:SOIC; Logic Function Number:92; No. of Channels:1; Operating Temperature Max:85°C; Operating Temperature Min:-40°C; Package / Case:SOIC; Supply Current:20mA; Supply Voltage Max:3.6V; Supply Voltage Min:3V; Termination Type:SMD
The DS92LV010A is one in a series of transceivers designed specifically for the high speed, low power proprietary bus backplane interfaces. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. To minimize bus loading the driver outputs and receiver inputs are internally connected. The logic interface provides maximum flexibility as 4 separate lines are provided (DIN, DE, RE, and ROUT). The device also features flow through which allows easy PCB routing for short stubs between the bus pins and the connector. The driver has 10 mA drive capability, allowing it to drive heavily loaded backplanes, with impedance as low as 27 Ohms. The driver translates between TTL levels (single-ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition the differential signaling provides common mode noise rejection of +-1V. The receiver threshold is +-100mV over a +-1V common mode range and translates the low voltage differential levels to standard (CMOS/TTL) levels.

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