Texas Instruments CDC516

the cdc516 is a high-performance low-skew low-jitter phase-lock loop clock driver. it uses a phase-lock loop (pll) to precisely align in both frequency and phase the feedback output (fbout) to the clock (clk) input signal. it is specifically designed for use with synchronous drams. the cdc516 operates at 3.3-v vcc and is designed to drive up to five clock loads per output. four banks of four outputs provide 16 low-skew low-jitter copies of the input clock. output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled separately via the 1g 2g 3g and 4g control inputs. when the g inputs are high the outputs switch in phase and frequency with clk; when the g inputs are low the outputs are disabled to the logic-low state. view all in datasheet