onsemi MC100EP809FAG

Low Skew Clock Driver, 100E Series, 9 True Output(s), 0 Inverted Output(s), ECL, PQFP32

Clock Driver, 2:1:9 Differential HSTL / PECL to HSTL, 3.3 V

MC100EP809FAG, CLOCK DRIVER HSTL, LVDS, PECL HSTL 2-INPUT, 32-PIN LQFP

Clock Drivers & Distribution 3.3V HSTL/PECL- HSTL Clk Driver w/LVTTL

The MC100EP809 is a low skew 1-to-9 differential bus clock driver designed with clock distribution in mind accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled the Output Enable (OE) which is LVTTL is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state. The MC100EP809 guarantees low output-to-output skew. The optimal design layout and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809s performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair.