onsemi 74VHCT74AM

Dual D-type Flip Flop With Preset And Clear | IC Ff D-type Dual 1 Bit 14SOIC
$ 0.154
Obsolete

가격 및 재고

데이터시트 및 문서

onsemi 74VHCT74AM에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

IHS

Datasheet9 페이지27년 전
Datasheet0 페이지0년 전

onsemi

Augswan

iiiC

Fairchild Semiconductor

재고 내역

3개월간의 트렌드:
Restocked

공급망

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1998-03-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2013-06-10
LTD Date2013-12-10

관련 부품

Texas InstrumentsSN74AHCT74QDRQ1
Automotive Catalog Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset 14-SOIC -40 to 125
Texas InstrumentsSN74AHCT74QDRG4Q1
Automotive Catalog Dual Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset 14-SOIC -40 to 125
Texas InstrumentsSN74AHCT74D
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 125
onsemi74F74SJX
Lead Free Set(Preset) and Reset D-Type Positive Edge Flip Flop 0C~70C TA 16mA 4.5V~5.5V 8ns
onsemi74F74SJ
Lead Free Set(Preset) and Reset D-Type Positive Edge Flip Flop 0C~70C TA 16mA 4.5V~5.5V 8ns
onsemiDM74AS74M
Lead Free Set(Preset) and Reset D-Type Positive Edge Flip Flop 0C~70C TA 16mA 4.5V~5.5V 9ns

설명

유통업체에서 제공한 onsemi 74VHCT74AM에 대한 설명입니다.

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR | IC FF D-TYPE DUAL 1BIT 14SOIC
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC N Rail
Tube e3 74VHCT MATTE TIN flip flop 3.9mm 4.5V 8.8ns @ 5V 50pF 140MHz
4.5V~5.5V 140MHz 8.8ns@5V,50pF D-Type 1 2 2uA SOP-14 Flip Flops ROHS
D Flip-Flop, AHCT/VHCT/VT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14
The VHCT74A is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC = 0V. These circuits prevent device destruction due to mismatched supply and input/output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup.

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