onsemi 74LVX74SJX

Lead Free Set(Preset) and Reset D-Type CMOS Flip Flop -40C~85C TA 2muA 4pF 2V~3.6V

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

2V~3.6V 85MHz 13.2ns@3.3V,50pF D-Type 1 2 2uA SO-14P Flip Flops ROHS

D Flip-Flop, LV/LV-A/LVX/H Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14

The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q#) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S#D (Set) sets Q to HIGH level LOW input to C#D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C#D and S#D makes both Q and Q# HIGH