onsemi 74LCX74SJ

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
$ 0.208
Obsolete

가격 및 재고

데이터시트 및 문서

onsemi 74LCX74SJ에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

IHS

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onsemi

Fairchild Semiconductor

Augswan

DigiKey

재고 내역

3개월간의 트렌드:
Restocked

공급망

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1996-01-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2013-06-10
LTD Date2013-12-10

관련 부품

Texas InstrumentsSN74LVC74ANSR
Dual positive-edge-triggered D-type flip-flops with clear and preset 14-SOP -40 to 125
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Texas InstrumentsSN74AHC74NSR
AHC/VHC/H/U/V SERIES DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP COMPLEMENTARY OUTPUT PDSO14
onsemi74LVX74SJ
Lead Free Set(Preset) and Reset D-Type CMOS Flip Flop -40C~85C TA 2muA 4pF 2V~3.6V
Texas InstrumentsSN74LVC112ANSR
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOP -40 to 125
onsemi74AC74SJ
D Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, CMOS, PDSO14

설명

유통업체에서 제공한 onsemi 74LCX74SJ에 대한 설명입니다.

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Lead Free Set(Preset) and Reset D-Type Positive Edge Flip Flop -40C~85C TA 10muA 7pF 2V~3.6V
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOP-II Rail
D Flip-Flop, LVC/LCX/Z Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14
2V~3.6V 150MHz 7ns@3.3V,50pF D-Type 1 2 10uA SO-14P Flip Flops ROHS
RAIL / EOL 3V DUAL D-TYPE FF 5V TOL INP
IC FF D-TYPE DOUBLE 1BIT 14-SOP
The LCX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q#) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S#D (Set) sets Q to HIGH level LOW input to C#D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C#D and S#D makes both Q and Q# HIGH

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