onsemi 74ACT377PC

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDIP20
$ 0.555
Obsolete

가격 및 재고

데이터시트 및 문서

onsemi 74ACT377PC에 대한 데이터시트 및 제조업체 설명서를 다운로드하세요.

IHS

Datasheet14 페이지27년 전
Datasheet13 페이지27년 전

DigiKey

SHENGYU ELECTRONICS

재고 내역

3개월간의 트렌드:
Restocked

공급망

Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1987-07-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)

관련 부품

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDIP20
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDIP20
NXP SemiconductorsN74F273AN,602
D Flip-Flop, F/FAST Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDIP20
Texas InstrumentsSN74ACT374N
Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs 20-PDIP -40 to 85
Texas InstrumentsSN74ABT374AN
Octal Edge-Triggered D-Type Flip-Flops with 3-State Outputs 20-PDIP -40 to 85
Texas InstrumentsSN74F377AN
Octal D-Type Flip-Flop With Clock Enable 20-PDIP 0 to 70

설명

유통업체에서 제공한 onsemi 74ACT377PC에 대한 설명입니다.

D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDIP20
4.5V~5.5V 175MHz 10ns@5V,50pF D-Type 8 1 40uA PDIP-20 Flip Flops ROHS
Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin PDIP W Rail
Tube e3 74ACT MATTE TIN flip flop 26.075mm 4.5V 10ns @ 5V 50pF 175MHz
IC FF D-TYPE SINGLE 8BIT 20PDIP
IC, 74ACT CMOS LOGICIC, 74ACT CMOS LOGIC; LOGIC IC FAMILY:ACT; LOGIC IC BASE NUMBER:74377; LOGIC IC FUNCTION:OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE; POSITIVE-EDGE TRIGGER; VOLTAGE, SUPPLY:5.5V; CASE STYLE:DIP; BASE NUMBER:74; GATES, RoHS Compliant: No
The AC/ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously,when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each Dinput, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

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