공급망
Harmonized Tariff Schedule (HTS) Code8542.31.00.60
Introduction Date2006-03-27
Lifecycle StatusProduction (Last Updated: 1 week ago)
관련 부품
Intel / AlteraEP2C20F256C8N
FPGA Cyclone« II Family 18752 Cells 402.58MHz 90nm Technology 1.2 Volt 256-Pin FBGA
Intel / AlteraEP2C20F256I8N
FPGA Cyclone® II Family 18752 Cells 402.58MHz 90nm Technology 1.2V 256-Pin FBGA
설명
유통업체에서 제공한 Intel / Altera EP2C20AF256I8N에 대한 설명입니다.
FPGA Cyclone® IIFamily 18752Cells 402.58MHz 1.2V 256-Pin FBGA Tray
ALTERA - EP2C20AF256I8N - FPGA,CYCLONE II, 20K ELEMENTS, FBGA256
Field Programmable Gate Array, 1172 CLBs, 402.5MHz, 18752-Cell, CMOS, PBGA256
FPGA, CYCLONE II, 20K ELEMENTS, FBGA256; No. of Logic Blocks: -; No. of Macrocells: 18752; FPGA Family: Cyclone II; Logic Case Style: BGA; No. of Pins: 256Pins; No. of Speed Grades: -; Total RAM Bits: 239616Kbit; No. of I/O's:
; Logic Type:EP2C20A; Logic Base Number:2; No. of I/O Pins:152; Termination Type:SMD; Package/Case:256-FBGA; No. of Pins:256; IC Generic Number:; Operating Temp. Max:100°C; Operating Temp. Min:-40°C ;RoHS Compliant: Yes
제조업체 별칭
Intel / Altera에는 유통업체가 대체하여 사용할 수 있는 전 세계 여러 브랜드가 있습니다. Intel / Altera는 다음 이름으로도 알려져 있습니다:
- Altera (Intel)
- Altera (Intel Programmable Solutions Group)
- Intel FPGAs/Altera
- ALTERA CORP
- Intel Corporation
- IntelProgrammable Solutions Group
- Intel / Alte
- INTEL CORP
- ALTERA CORPORATION
- ALTERAINERNATIONALLIMITED
기술 사양
Physical
Case/PackageFBGA
MountSurface Mount
Number of Pins256
Number of Terminals256
Technical
Max Frequency402.5 MHz
Max Operating Temperature100 °C
Max Supply Voltage1.25 V
Memory Size29.3 kB
Min Operating Temperature-40 °C
Min Supply Voltage1.15 V
Number of I/Os152
Number of Inputs152
Number of Logic Blocks (LABs)1172
Number of Logic Elements/Cells18752
Number of Macrocells18752
Number of Outputs136
Operating Supply Voltage1.2 V
Speed Grade8
Dimensions
Height - Seated (Max)1.55 mm
Length17 mm
Terminal Pitch1 mm
Width17 mm
규정 준수
환경 분류
China RoHSCompliant
Lead FreeLead Free
Radiation HardeningNo
REACH SVHCYes
RoHSCompliant
규정 준수 정책