the cdclvp2102 is a highly versatile low additive jitter buffer that can generate four copies of lvpecl clock outputs from two lvpecl lvds or lvcmos inputs for a variety of communication applications. it has a maximum clock frequency up to 2 ghz. each buffer block consists of one input that feeds two lvpecl outputs. the overall additive jitter performance is less than 0.1 ps rms from 10 khz to 20 mhz and overall output skew is as low as 10 ps making the device a perfect choice for use in demanding applications. the cdclvp2102 clock buffer distributes two clock inputs (in0 in1) to four pairs of differential lvpecl clock outputs (out0 out3) with minimum skew for clock distribution. each buffer block consists of one input that feeds two lvpecl clock outputs. view all in datasheet