the cdclvp1102 is a highly versatile low additive jitter buffer that can generate two copies of lvpecl clock outputs from one lvpecl lvds or lvcmos input for a variety of communication applications. it has a maximum clock frequency up to 2 ghz. the overall additive jitter performance is less than 0.1 ps rms from 10 khz to 20 mhz and overall output skew is as low as 10 ps making the device a perfect choice for use in demanding applications. the cdclvp1102 clock buffer distributes a single clock input (in) to two pairs of differential lvpecl clock outputs (out0 out1) with minimum skew for clock distribution. the inputs can be lvpecl lvds or lvcmos/lvttl. the cdclvp1102 is specifically designed for driving 50- transmission lines. view all in datasheet