Texas Instruments CDCL1810

the cdcl1810 is a high-performance clock distributor. the programmable dividers p0 and p1 give a high flexibility to the ratio of the output frequency to the input frequency: fout = fin/p where: p (p0 p1) = 1 2 4 5 8 10 16 20 32 40 80 the cdcl1810 supports one differential lvds clock input and a total of 10 differential cml outputs. the cml outputs are compatible with lvds receivers if they are ac-coupled. with careful observation of the input voltage swing and common-mode voltage limits the cdcl1810 can support a single-ended clock input as outlined in the pin table. all device settings are programmable through the sda/scl serial two-wire interface. the phase of one output group relative to the other can be adjusted through the sda/scl interface. view all in datasheet