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onsemi MM74HC74ASJX

4¦ÌA 19ns@ 6V, 50pF Complimentary 2 2V 6V 5.2mA Set(Preset) and Reset 5pF 5.2mA 94MHz SOP-14
$ 0.425
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データシート & ドキュメント

onsemi MM74HC74ASJXのデータシートとメーカー資料をダウンロードする。

IHS

Datasheet11ページ27年前
Datasheet0ページ0年前

onsemi

Augswan

Fairchild Semiconductor

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サプライチェーン

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1998-01-01
Lifecycle StatusProduction (Last Updated: 6 years ago)
Manufacturer Lifecycle StatusLIFETIME (Last Updated: 6 years ago)

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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 14-SOP 0 to 70

説明

onsemi MM74HC74ASJXの詳細は販売業者から提供されます。

4¦ÌA 19ns@ 6V,50pF Complimentary 2 2V 6V 5.2mA Set(Preset) and Reset 5pF 5.2mA 94MHz SOP-14
Dual D-Type Flip-Flop with Preset and Clear
D Flip-Flop, HC/UH Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMOS, PDSO14
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOP-II T/R
2V~6V 94MHz 19ns@6V,50pF D-Type 1 2 4uA SOP-14 Flip Flops ROHS
Flip Flops Dl D-Type Flip-Flop
IC FF D-TYPE DOUBLE 1BIT 14-SOP
DUAL D F/F W/PRESET AND CLEARQ
The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part. It possesses the high noise immu-nity and low power consumption of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. This flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive-going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. The 74HC logic family is functionally and pin out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V CC and ground.

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