onsemi MM74HC373N

8¦ÌA 19ns 1 2V 6V 7.8mA D-Type Transparent Latch HC 7.8mA PDIP-20 26.92mm*7.11mm*3.43mm
$ 0.629
Obsolete

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データシート & ドキュメント

onsemi MM74HC373Nのデータシートとメーカー資料をダウンロードする。

IHS

Datasheet9ページ3年前
Datasheet8ページ21年前

JRH Electronics

onsemi

Augswan

Fairchild Semiconductor

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サプライチェーン

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1983-01-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2011-03-02
LTD Date2011-09-02

関連部品

Texas InstrumentsSN74HC273N
FLIP-FLOP, OCTAL D; OCTAL D TYPE FLIP-FLOP WITH CLEAR; 0 TO 5 V; PDIP; -40 DEGC
Texas InstrumentsSN74AC534N
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-PDIP -40 to 85
Flip Flop D-Type Bus Interface Pos-Edge 3-ST 1-Element 20-Pin PDIP Rail
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDIP20
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20
Texas InstrumentsCD74HC174E
Flip Flop D-Primary-Secondary Type Pos-Edge 1-Element 16-Pin PDIP Tube

説明

onsemi MM74HC373Nの詳細は販売業者から提供されます。

8¦ÌA 19ns 1 2V 6V 7.8mA D-Type Transparent Latch HC 7.8mA PDIP-20 26.92mm*7.11mm*3.43mm
Latch, Octal Transparent D-Type Latch, 0 to 5 V, 500 ns (Max.) @ 4.5 V, PDIP-N
IC, 74HC CMOS, 74HC373, DIP20, 6V; Latch Type:D Type; Output Current:7.8mA; Propagation Delay:18ns; No. of Bits:8; IC Output Type:Tri State; Supply Voltage Range:2V to 6V; Logic Case Style:DIP; No. of Pins:20; Operating Temperature Range:-40°C to +85°C; SVHC:No SVHC (19-Dec-2011); Base Number:74; Device Marking:74HC373; IC Generic Number:74HC373; Logic Function Number:373; Logic IC Base Number:74373; Logic IC Family:HC; Logic IC Function:Octal D-Type Transparent Latch (3-State); No. of Gates:8; No. of Inputs:1; Operating Temperature Max:85°C; Operating Temperature Min:-40°C; Output Type:Tri State; Package / Case:DIP; Supply Voltage:6V; Supply Voltage Max:6V; Supply Voltage Min:2V; Termination Type:Through Hole
The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

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