onsemi 74VHC112SJX

Tape & Reel (TR) e3 74VHC MATTE TIN flip flop 5.3mm 2V 10.5ns @ 5V 50pF 185MHz
$ 0.241
Obsolete

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データシート & ドキュメント

onsemi 74VHC112SJXのデータシートとメーカー資料をダウンロードする。

IHS

Datasheet9ページ19年前
Datasheet0ページ0年前

onsemi

SHENGYU ELECTRONICS

Fairchild Semiconductor

DigiKey

在庫履歴

3か月間の傾向:
Restocked

サプライチェーン

Export Control Classification Number (ECCN) CodeEAR99
Harmonized Tariff Schedule (HTS) Code8542.39.00.01
Introduction Date1996-09-01
Lifecycle StatusObsolete (Last Updated: 4 months ago)
LTB Date2010-09-23
LTD Date2011-03-23

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Tape & Reel (TR) 74VHC112 e3 74VHC flip flop 9.9mm 2V 10.5ns @ 5V 50pF 185MHz
Texas InstrumentsSN74HC112DR
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85
2V~3.6V 150MHz 15ns@3.3V,50pF JK-Type 1 2 2uA SO-16P Flip Flops ROHS
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Texas InstrumentsSN74AHC74DR
Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC T/R / IC D-TYPE POS TRG DUAL 14SOIC

説明

onsemi 74VHC112SJXの詳細は販売業者から提供されます。

Tape & Reel (TR) e3 74VHC MATTE TIN flip flop 5.3mm 2V 10.5ns @ 5V 50pF 185MHz
J-K Flip-Flop, AHC/VHC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16
2V~5.5V 185MHz 10.5ns@5V,50pF JK-Type 1 2 2uA SO-16P Flip Flops ROHS
Dual J-K Flip-Flops with Preset and Clear
2¦ÌA 10.5ns@ 5V,50pF , Complimentary 2 2V 5.5V 8mA Set(Preset) and Reset VHC 4pF 8mA 185MHz SOP-16 , 10.2mm*5.3mm*1.8mm
IC FF JK TYPE DOUBLE 1BIT 16SOP
The VHC112 is an advanced high speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. The LOW signal on PR or CLR prevents clocking and forces Q and Q# HIGH, respectively. Simultaneous LOW signals on PR and CLR force both Q and Q# HIGH. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

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