Texas Instruments SN74ACT3622-20PCB

FIFO Mem Sync Dual Bi-Dir 256 x 36 x 2 120-Pin HLQFP EP Tray

74ACT3622 Width Tray 74ACT fifo memory 50MHz 400muA 0.4mm 13ns

IC CLK DUAL FIFO MEMORY 120HLQFP / Synchronous FIFO 18K (256 x 36 x 2) Bi-Directional 50MHz 13ns 120-HLQFP (14x14)

256 X 36 BI-DIRECTIONAL FIFO 13 ns PQFP120

IC CLK DUAL FIFO MEMORY 120HLQFP

IC FIFO SYNC 256X36X2 120HLQFP

The SN74ACT3622 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 67 MHz with read access times of 11 ns. Two independent 256 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags almost full (AF\) and almost empty (AE\) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider datapaths. The SN74ACT3622 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The input-ready (IRA, IRB) flag and almost-full (AFA\, AFB\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA\, AEB\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the AF\ and AE\ flags of the FIFO can be programmed from port A. The SN74ACT3622 is characterized for operation from 0C to 70C. For more information on this device family, see the application report FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) and Metastability Performance of Clocked FIFOs (literature number SCZA004).