Texas Instruments CDCVF855

The CDCVF855 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLKY[0:3]FBOUTCLKFBINPWRDWNPWRDWN

the cdcvf855 is a high-performance low-skew low-jitter zero-delay buffer that distributes a differential clock input pair (clk clk) to 4 differential pairs of clock outputs (y[0:3] y[0:3]) and one differential pair of feedback clock outputs (fbout fbout). the clock outputs are controlled by the clock inputs (clk clk) the feedback clocks (fbin fbin) and the analog power input (avdd). when pwrdwn is high the outputs switch in phase and frequency with clk. when pwrdwn is low all outputs are disabled to a high-impedance state (3-state) and the pll is shut down (low-power mode). the device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 mhz (typical 10 mhz). view all in datasheet