Infineon IRS2113PBF

600 V high-side and low-side gate driver IC with shutdown, PDIP14, RoHS

Tube IRS2113PBF Half-Bridge 1996 gate driver 35ns -40C~150C TJ 2.5A 2.5A 1.6W

IRS2113 Series 600 V 2.5 A 20 V Supply Dual High And Low Side Driver - PDIP-14

Power MOSFET and IGBT Driver, Hi/Lo Side, 600V, 2A, 14-pin PDIP, Tube

Half Bridge Based IGBT/MOSFET Driver, 2.5A, CMOS, PDIP14

High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High Creepage

No. of Channels:2Channels; Driver Configuration:High Side and Low Side; Power Switch Type:IGBT, MOSFET; No. of Pins:14Pins; Driver Case Style:DIP; Input Type:Non-Inverting; Source Current:2.5A; Sink Current:2.5A; Input Delay:130ns RoHS Compliant: Yes

IC, DRIVER, HIGH/LOW SIDE, DIP14; Device Type:MOSFET; Module Configuration:High Side / Low Side; Peak Output Current:2.5A; Input Delay:130ns; Output Delay:120ns; Supply Voltage Range:10V to 20V; Driver Case Style:DIP; No. of Pins:14; Operating Temperature Range:-40°C to +125°C; SVHC:No SVHC (19-Dec-2011); Base Number:2113; No. of Outputs:2; Operating Temperature Max:125°C; Operating Temperature Min:-40°C; Output Current:2.5A; Output Current + Max:2A; Output Sink Current Min:2000mA; Output Source Current Min:2000mA; Output Voltage:620V; Output Voltage Max:20V; Package / Case:DIP; Power Dissipation Pd:1.6W; Supply Voltage Max:20V; Supply Voltage Min:10V; Termination Type:Through Hole

600 V High and Low Side Driver IC with typical 2.5 A source and 2.5 A sink currents in 14 Lead PDIP package for IGBTs and MOSFETs. Also available in x16 Lead SOICWB and 14 Lead MLPQ 4x4. | Summary of Features: Floating gate driver designed for bootstrap operation; Fully operational to +600 V; Fully operational to +500 V option available (IRS2110 ); Tolerant to negative transient voltage, dV/dt immune; Gate drive supply range from 10 V to 20 V; Undervoltage lockout for both channels; 3.3 V logic compatible; Separate logic supply range from 3.3 V to 20 V; Logic and power ground +/- 5 V offset; CMOS Schmitt-triggered inputs with pull-down; Cycle by cycle edge-triggered shutdown logic; Matched propagation delay for both channels; Outputs in phase with inputs