Infineon IRS2112PBF

600 V high-side and low-side gate driver IC with shutdown, PDIP14, RoHS

Tube IRS2112PBF Half-Bridge 1996 gate driver 130ns -40C~150C TJ 290mA 600mA 1.6W

HIGH AND LOW SIDE DRIVER Buffer/Inverter Based Peripheral Driver, CMOS, PDIP14

Power MOSFET and IGBT Driver, Hi/Lo Side, 600V, 14-pin PDIP, Tube

Half Bridge Based IGBT/MOSFET Driver, 0.6A, CMOS, PDIP14

MOSFET Driver IC; Device Type:High and Low Side; No. of Outputs:2; Output Voltage:620V; Output Current:600mA; Power Dissipation, Pd:1.6W; Supply Voltage Min:10V; Supply Voltage Max:25V; Termination Type:Through Hole ;RoHS Compliant: Yes

Type = High Side / Type = Low Side / Outputs = 2 / Configuration = Non-Inverting / Rise Time ns = 75 / Fall Time ns = 35 / Output Current mA = 600 / Supply Voltage Min. V = 10 / Supply Voltage Max. V = 20 / Operating Temperature Min. °C = -40 / Operating Temperature Max. °C = 125 / Package Type = PDIP / Pins = 14 / Mounting Type = Through Hole / Packaging = Tube / Length mm = 20.19 / Width mm = 7.62 / Height mm = 4.94

IC, HIGH, LOW SIDE DRIVER, DIP14; Device Type:MOSFET; Module Configuration:High Side / Low Side; Peak Output Current:600mA; Input Delay:135ns; Output Delay:105ns; Supply Voltage Range:10V to 20V; Driver Case Style:DIP; No. of Pins:14; Operating Temperature Range:-40°C to +125°C; SVHC:No SVHC (20-Jun-2011); Base Number:2112; No. of Outputs:2; Output Sink Current:600mA; Output Source Current Max:290mA; Output Voltage:620V; Package / Case:DIP; Supply Voltage Max:20V; Supply Voltage Min:10V; Termination Type:Through Hole

600 V High and Low Side Driver IC with typical 0.29 A source and 0.6 A sink currents in 14 Lead PDIP package for IGBTs and MOSFETs. Also available in 16 Lead SOICWB. | Summary of Features: Floating gate driver designed for bootstrap operation; Fully operational to +600 V; Tolerant to negative transient voltage, dV/dt immune; Gate drive supply range from 10 V to 20 V; Undervoltage lockout for both channels; 3.3 V logic compatible; Separate logic supply range from 3.3 V to 20 V; Logic and power ground +/- 5 V offset; CMOS Schmitt-triggered inputs with pull-down; Cycle by cycle edge-triggered shutdown logic; Matched propagation delay for both channels; Outputs in phase with inputs