Texas Instruments TL16PC564BLVPZ

IC PCMCIA UART 100LQFP "UART IC 1, UART Channel 64 Byte 100-LQFP (14x14)"

PCMCIA-to-UART 1-CH 64byte FIFO 3V/5V 100-Pin LQFP

Tray S-PQFP-G100 ALSO OPERATES AT 3V SUPPLY 0.0140380859375MBps interface UART 70C 14mm 60MHz 64Byte

Differential Drivers and Receiver 16-Pin PDIP Tube

Contains Lead GULL WING SERIAL IO/COMMUNICATION CONTROLLER SERIAL Obsolete UART IC 2.7V~3.3V 1Mbps 64Byte 60MHz

UARTs PCMCIA Univ Async Receiver Transmitter

The TL16PC564B/BLV is designed to provide all the functions necessary for a Personal Computer Memory Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface. This interface provides a serial-to-parallel conversion for data to and from a modem coder-decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element (ACE) interface at any point in the operation. Reported status information includes the type of transfer operation in process, the status of the operation, and any error conditions encountered. Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute memory is initialized by the subsystem. The TL16PC564B/BLV uses a TL16C550 ACE-type core with an expanded 64 11 receiver first-in-first-out (FIFO) memory and a 64 8 transmitter FIFO memory. The receiver trigger logic flags have been adjusted in order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows the subsystem to read UART status information. A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt operation is not affected in this mode.