Texas Instruments SN74AS646

these devices consist of bus-transceiver circuits with 3-state or open-collector outputs d-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. data on the a or b bus is clocked into the registers on the low-to-high transition of the appropriate clock (clkab or clkba) input. figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers. output-enable () and direction-control (dir) inputs control the transceiver functions. in the transceiver mode data present at the high-impedance port may be stored in either or both registers. view all in datasheet