onsemi MC74VHC74DR2G

74VHC Series Dual Type-D Flip-Flop with Set and Reset SMT - SOIC 14
$ 0.149
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Datasheet8 SeitenVor 7 Jahren

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Alternative Teile

Price @ 1000
$ 0.149
$ 0.077
$ 0.077
Stock
574,523
347,213
347,213
Authorized Distributors
6
2
2
Case/Package
SOP
SOP
SOP
Number of Pins
14
14
14
Logic Function
AND, D-Type, Flip-Flop
AND, D-Type, Flip-Flop
AND, D-Type, Flip-Flop
Number of Elements
2
2
2
Number of Bits per Element
1
1
1
Propagation Delay
10.5 ns
10.5 ns
10.5 ns
Frequency
75 MHz
75 MHz
75 MHz
Clock Edge Trigger Type
Positive Edge
Positive Edge
Positive Edge
Min Supply Voltage
2 V
2 V
2 V
Max Supply Voltage
5.5 V
5.5 V
5.5 V
Quiescent Current
2 µA
-
-

Lieferkette

Country of OriginMainland China, Philippines, Thailand
Harmonized Tariff Schedule (HTS) Code8542.39.00.60
Introduction Date1997-06-01
Lifecycle StatusProduction (Last Updated: 5 years ago)
Manufacturer Lifecycle StatusACTIVE (Last Updated: 5 years ago)

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74VHC Series High Speed CMOS Dual D-Type Flip-Flop w/ Preset and Clear - SOIC-14
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Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 125
Texas InstrumentsSN74LV74ADR
Flip Flop D-Type Pos-Edge Push-Pull 2-Element 14-Pin SOIC T/R
Tape & Reel (TR) 74LVX74 74LVX Non-Inverting flip flop 8.75mm 13.2ns @ 3.3V 50pF 85MHz 22ns

Beschreibungen

Beschreibungen von onsemi MC74VHC74DR2G, die von den Distributoren bereitgestellt werden.

74VHC Series Dual Type-D Flip-Flop with Set and Reset SMT - SOIC 14
Flip Flop D-Type Pos-Edge 2-Element Automotive 14-Pin SOIC N T/R
Tape & Reel (TR) 74VHC74 e3 74VHC flip flop 8.65mm 2V 9.3ns @ 5V 50pF 115MHz
D FLIP FLOP W/ SET/RESET, DUAL, SOIC-14; Logic Family / Base Number: 74VHC74; Flip-Flop Type: D; Propagation Delay: 9.3ns; Frequency: 170MHz; Output Current: -; Logic Case Style: SOIC; No. of Pins: 14Pins; Trigger Type: Positive
The MC74VHC74 is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse. Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low. The internal circuit is composed of three stages including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

Aliasnamen des Herstellers

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  • ONS
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  • ON SEM
  • ON SEMICONDUCTO
  • ON SEMICONDUCTORS
  • ONSEMIC
  • ON Semicondu
  • OSC
  • ONSE
  • ON SEMICOND
  • ON Semiconductor / Fairchild
  • SCG
  • ON Semiconductor Cor
  • ON SEMICO
  • ONSM
  • ON SEMICONDUCTOR CORP
  • onsemi / Fairchild
  • MOT/ON SEMI
  • Fairchild/ONSemiconductor
  • ON Semiconductor Corporation
  • ON4
  • ON Semi - ON Semiconductor
  • ON SEMICONDUCT
  • ON-SEMI SCG
  • ON Semiconductor Inc.
  • onsemiconductor
  • On Semiconductor Ltd