onsemi MC10H646FNG

Low Skew Clock Driver, 10H Series, 8 True Output(s), 0 Inverted Output(s), ECL, PQCC28

PECL TTL MC10H646 28-LCC (J-Lead) Obsolete clock buffer 4.57mm 0.024A 0.5ns 80MHz

Clock Multiplexer 8-OUT 28-Pin PLCC Rail

low skew translating clock driver

PECL/TTL-TTL 1:8 Distribution Chip

IC CLK BUFFER 2:8 80MHZ 28PLCC

MC10H646FNG, MOTOR DRIVERS / CONTROLLERS;

The MC10H/100H646 is a single supply low skew translating 1:8 clock driver. Devices in the H600 translator series utilize the 28-lead PLCC for optimal power pinning signal flow through and electrical performance. The single supply H646 is similar to the H643 which is a dual supply 1:8 version of the same function. The H646 was designed specifically to drive series terminated transmission lines. Special techniques were used to match the HIGH and LOW output impedances to about 7ohms. This simplifies the choice of the termination resistor for series terminated applications. To match the HIGH and LOW output impedances it was necessary to remove the standard IOS limiting resistor. As a result the user should take care in preventing an output short to ground as the part will be permanently damaged. The H646 device meets all of the requirements for driving the 60 and 66MHz Pentium Microprocessor components which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for point-to-point clock distribution to simplify board layout and optimize signal integrity. The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to TTL loads on a daughter board. When used in conjunction with the MC10/100E11 designed. In addition a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single chip. For correct operation the unused input pins should be left open. The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied. The output buffers of the H646 can drive two series terminated 50 transmission lines each. This capability allows the to drive up to 16 different point-to-point clock loads. Refer to the Applications section for a more detailed discussion in this area. The 10H version is compatible with MECL 10H ECL logic levels. The 100H