onsemi MC100EP195BFAG

32-LQFP 100EP e3 NECL MODE: VCC=0WITH VEE=-3.0V TO -3.6V delay line circuit 7mm 2.5ns 3V 5Weeks

Active Delay Line, Programmable, 1-Func, 1023-Tap, Complementary Output, ECL, PQFP32

Active Programmable Delay Line 1-IN 0.01ns ABS 12.2ns MAX 32-Pin LQFP Frame

PROG DELAY LINE, 2.2NS, LQFP-32; Total Delay Time: 12.2ns; Delay Time per Tap: 2.2ns; No. of Taps: 1024; Supply Voltage Min: 3V; Supply Voltage Max: 3.6V; Digital IC Case: LQFP; No. of Pins: 32Pins; Operating Temperature Min: -4

Programmable Delay Chip 1024Tap 12.2Ns Lqfp32; No. De Derivaciones:1024; Tiempo De Retraso Por Derivación:2.2Ns; Tiempo De Retardo, Total:12.2Ns; Tensión De Alimentación Mín.:3V; Tensión De Alimentación Máx.:3.6V |Onsemi MC100EP195BFAG

The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(9:0) values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D(9:0). A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D(10:0). The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.