onsemi FAN3278TMX

IC GATE DRVR HALF-BRIDGE 8SOIC / Half-Bridge Gate Driver IC Inverting, Non-Inverting 8-SOIC

Low-Voltage 27-V PMOS-NMOS Bridge Driver - 8LD, SOIC,JEDEC MS-012, .150" NARROW BODY

Tape & Reel (TR) FAN3278 Half-Bridge 2017 gate driver 17ns 125C 1A 1.5A 308mW

FAN3278 Series 27 V 1.5 A Surface Mount Dual PMOS-NMOS Bridge Driver - SOIC-8

Driver 1.5A 2-OUT High and Low Side Half Brdg Inv/Non-Inv 8-Pin SOIC T/R

onsemi 8PinMOSFETDriver, 27VPower, SOICencapsulation, NMOSbridge、PMOSbridge

MOSFET DRIVER, LOW/HIGH SIDE, SOIC-8; Driver Configuration: High Side and Low Side; Peak Output Current: 1.5A; Supply Voltage Min: 8V; Supply Voltage Max: 27V; Driver Case Style: SOIC; No. of Pins: 8Pins; Input Delay: 70ns; Out

The FAN3278 dual 1.5A gate driver is optimized to drive a high-side P-channel MOSFET and a low-side N-channel MOSFET in motor control applications operating from a voltage rail up to 27V. Internal circuitry limits the voltage applied to the gates of the external MOSFETs to 13V maximum. The driver has TTL input thresholds and provides buffer and level translation from logic inputs. Internal circuitry prevents the output switching devices from operating if the VDD supply voltage is below the IC operation level. Internal 100kΩ resistors bias the non-inverting output LOW and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. The FAN3278 driver incorporates MOSFET devices for the final output stage, providing high current throughout the MOSFET turn-on / turn-off transition to minimize switching loss. The internal gate-drive regulators provide optimum gate-drive voltage when operating from a rail of 8V to 27V. The FAN3278 can be driven from a voltage rail of less than 8V; however, its gate drive current is reduced. The FAN3278 has two independent ENABLE pins that default to ON if not connected. If the ENABLE pin for non-inverting channel A is pulled LOW, OUTA is forced LOW. If the ENABLE pin for inverting channel B is pulled LOW, OUTB is forced HIGH. If an input is left unconnected, internal resistors bias the inputs such that the external MOSFETs are OFF.