Analog Devices ADRF6820ACPZ-R7

Internal LO frequency range | RF DEMOD IC 695MZ-2.7GHZ 40LFCSP

TELECOM CIRCUIT; Temperature Grade: INDUSTRIAL; Terminal Form: NO LEAD; No. of Terminals: 40; Package Code: HVQCCN; Package Shape: SQUARE;

The ADRF6820 is a highly integrated demodulator and synthesizer ideally suited for next generation communication systems. The feature rich device consists of a high linearity broadband I/Q demodulator, an integrated fractional-N phase-locked loop (PLL), and a low phase noise multicore, voltage controlled oscillator (VCO). The ADRF6820 also integrates a 2:1 RF switch, an on-chip tunable RF balun, a programmable RF attenuator, and two low dropout (LDO) regulators. This highly integrated device fits within a small 6 mm × 6 mm footprint. The high isolation 2:1 RF switch and on-chip tunable RF balun enable the ADRF6820 to support two single-ended, 50 Ω terminated RF inputs. A programmable attenuator ensures an optimal differential RF input level to the high linearity demodulator core. The integrated attenuator offers an attenuation range of 0 dB to 15 dB with a step size of 1 dB. The ADRF6820 offers two alternatives for generating the differential local oscillator (LO) input signal: externally via a high frequency, low phase noise LO signal or internally via the on-chip fractional-N synthesizer. The integrated synthesizer enables continuous LO coverage from 356.25 MHz to 2850 MHz. The PLL reference input can support a wide frequency range because the divide or multiplication blocks can increase or decrease the reference frequency to the desired value before it is passed to the phase frequency detector (PFD). When selected, the output of the internal fractional-N synthesizer is applied to a divide-by-2 quadrature phase splitter. From the external LO path, a 1× LO signal can be applied to the built-in polyphase filter, or a 2× LO signal can be used with the divide-by-2 quadrature phase splitter to generate the quadrature LO inputs to the mixers. The ADRF6820 is fabricated using an advanced silicon-germanium BiCMOS process. It is available in a 40-lead, RoHS-compliant, 6 mm × 6 mm LFCSP package with an exposed paddle. Performance is specified over the −40°C to +85°C temperature range. APPLICATIONS Cellular W-CDMA/GSM/LTE Digital predistortion (DPD) receivers Microwave point-to-point radios